1. Field of the Invention
The present invention relates to a digital receiver, and more particularly, to an apparatus for extracting specific channel data from multi-channel discrete time data.
2. Description of the Related Art
A digital receiver receives discrete time data converted from a multi-channel analog signal through an analog-to-digital (A/D) converter and extracts desired channel data therefrom.
As illustrated in FIG. 1, a conventional digital receiver includes multipliers 10 and 12, a local oscillator 14, and a low pass filter (LPF) 16. The LPF 16 may be a decimating low pass FIR (Finite Impulse Response) filter.
In operation, an input signal S[n] applied to an input terminal of the digital receiver is a digital signal consisting of an I channel component and a Q channel component. An example of the input signal S[n] can be given by: EQU S[n]=I[n].multidot.cos W.sub.s n+Q[n].multidot.sin W.sub.s n (1)
where I[n].multidot.cos W.sub.s n and I[n].multidot.sin W.sub.s n denote the I channel component and the Q channel component, respectively.
The input signal S[n] is multiplied through the multipliers 10 and 12 by intermediate frequency signals sin[W.sub.s n] and cos[W.sub.s n], respectively. The multipliers 10,12 generate both a baseband signal and a high frequency signal. The intermediate frequency signals cos[W.sub.s n] and sin[W.sub.s n] are produced from the local oscillator 14. The baseband signal and the high frequency signal generated from the multipliers 10 and 12 are supplied to the LPF 16 which removes the high frequency component and passes only the baseband signal that the user desires to receive.
In the above structure of the digital receiver, since the input signal S[n] is a sampled digitally converted signal, the multipliers 10 and 12 should have the same data processing rate as a sampling rate of the input signal S[n]. If the sampling rate of the input signal S[n] is high, then multipliers 10 and 12 must be high speed devices so as to process the input signal S[n] with a high sampling rate. This presents a disadvantage in that if the digital receiver is achieved by using a commercially available DSP (Digital Signal Processor) chip, a high-speed multiplier must be provided in the DSP chip. Even though such multipliers can be achieved on an integrated circuit chip, the complicated multiplier has an adverse effect on other processors, and thus a single DSP chip cannot be used.